Dram with segmented page configuration

ABSTRACT

This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.

BACKGROUND

Conventional dynamic random access memory (DRAM) arrays have a largepage size—the number of bits that are read into sense amplifiers duringrow activate operations. The large page size, typically 8,192 bits, isbeneficial in that it allows the entire array to be refreshed with feweroperations. On the other hand the large page size can result inconsiderable wasted energy. One example of unnecessary energyexpenditure is a read operation in which, as typically is the case, onlya small number (4-32) of the bits in the page are of interest. Despitethis, all of the bit lines in the page are charged and discharged toperform such a read in conventional DRAMs. So energy is expended to readthe entire page when data from only a portion of the page is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows an exemplary dynamic random access memory(DRAM) array according to the present description, having a segmentedpage configuration.

FIG. 2 schematically depicts a column and associated structures of theDRAM array of FIG. 1.

DETAILED DESCRIPTION

This description is directed to a dynamic random access memory (DRAM)array which can be operated in a more energy efficient manner. The DRAMarray is organized as a matrix of cells in rows and columns, such thateach cell is uniquely associated with a specific row and column. TheDRAM array has a width, also referred to as the page width, which isequal to the number of columns in the array. The DRAM array isconfigured so that certain operations can be implemented so as to affectonly some of the columns, or only a portion of the width of the array.For example, the rows of the array may have segmented word lines, sothat each row has multiple local word lines. Instead of activating theentire row and thereby expending energy to read and restore bits thatmay not be of interest (i.e., wasted energy due to “overfetch,”) one ormore selected local word lines may be used to select and read only thosecells associated with the local word lines. The columns associated withthe non-selected local word lines are not used, providing an energysavings over what would be expended if all of the columns were used.Specifically, the bit lines of those non-selected columns do not need tobe charged and discharged to perform the targeted read. Nor do the cellsand dummy cells for those columns need to be restored.

FIG. 1 shows an exemplary DRAM array 100 according to the presentdescription. DRAM array 100 includes storage cells arranged in a matrixof rows and columns, such that each storage cell is uniquely associatedwith a specific row and column. In the example of FIG. 1, the array hasr rows, one of which is indicated at 102 in the figure, and 8192 columns(eight kilobit page size). The 8192 columns are grouped into 32 groupsor “subpages” of 256 columns each. The vertical stack of elements headedby each box labeled “dummy cells” corresponds to one of the 32 groups of256 columns. Therefore, each column has r cells (the number of rows inthe array) and each row has 8192 cells (the number of columns in thearray). Where dummy cells are employed, each column will also have twodummy cells, one even and one odd. The specific numbers of rows,columns, cells and columns per group are arbitrary in the example; othernumbers may be employed as appropriate to the implementation.

FIG. 2 schematically shows an example column 200 of DRAM array 100.Column 200 includes a pair of bit lines—even bit line 202 and odd bitline 204—that are coupled to sense amplifier 206. The figure shows sixcells: four regular storage cells 208 and two dummy cells 210. Each cell208 has a capacitor 212 coupled to one of the bit lines via a transistor214 that is gate-coupled to a word line 216 that is asserted to turn onthe transistor. Cells 208 a and 208 c are coupled to even bit line 202,and cells 208 b and 208 d are coupled to odd bit line 204. Cells 208 aand 208 c may therefore be referred to as “even cells,” and cells 208 band 208 d as “odd cells.” Their associated word lines may be designatedsimilarly, i.e., 216 a and 216 c are even word lines and 216 b and 216 dare odd word lines.

Dummy cells 210 include similar configurations of capacitors 220,transistors 222 and word lines 224. Dummy cell 210 a is coupled to evenbit line 202, and it and its dummy word line 224 a may therefore bereferred to as “even.” Dummy cell 210 b and dummy word line 224 b inturn are “odd.”

Prior to reading the logical HI or logical LO values stored in thecells, bit lines 202 and 204, and dummy cells 210, are precharged to 50%of the logical HI voltage. For simplicity, logical HI and logical LOwill be referred to herein as Vdd and Vss, respectively. A row is thenactivated by asserting one of the word lines 216 so as to turn on thetransistor and cause the logical HI or LO voltage stored on the cellcapacitor to be shared with the pre-charged bit line. Typically thecapacitance of the bit line is relatively high compared to thecapacitance of the cell. Accordingly, if the stored value is HI, theresulting voltage on the bit line after charge sharing will he slightlyhigher than the precharged 50% value (Vdd/2 plus a small amount). If thestored value is LO (Vss), then the resulting voltage after chargesharing will be slightly less than the 50% value (Vdd/2 minus a smallamount).

At the same time that the specific word line 216 is asserted, acomplementary dummy word line 224 is asserted. In other words, if aneven row is activated (line 216 a or 216 c), then the odd dummy line 224b is asserted to cause the odd dummy cell to share charge onto theprecharged odd bit line 204, and vice versa.

At this point, one of the bit lines is slightly above or below Vdd/2,respectively reflecting whether the stored value in the cell was HI orLO, and the other is at Vdd/2 due to precharge and the Vdd/2 value onthe dummy cell capacitor. There may be some movement due to noise andother factors, but the use of the dummy cell facilitates producing anaccurately measurable differential signal on the bit lines in the faceof noise and other issues. The sense amplifier is then triggered tocapture the differential signal and convert the small differential intoa logical HI or LO output, depending on the value that was on thestorage cell capacitor. The column may also optionally include a latch226 to provide an additional bit of storage. For example a value may beheld active in the latch while refresh or precharge operations are beingperformed that affect the sense amplifier. In addition to capturing thedifferential signal, the sense amplifier also drives the bit line fullswing to restore the capacitor to its charge level existing just priorto the destructive read. Once the charge is restored across the cellcapacitor, the cell's word line is lowered.

Returning now to FIG. 1, DRAM array 100 is configured so that certainDRAM commands affect only a selected portion of the width of the array.In terms of the array's columns, control may be implemented to controlwhich columns of the DRAM array are involved during word lineassertions, bit line precharge, sense amp operation, latch control,column selection and other commanded DRAM operations. In terms of agiven row, this control may be understood as creating a condition inwhich a DRAM command affects only a portion of the row.

DRAM array 100 includes 32 subpages, designated “Subpage 0” through“Subpage 31” at the top of the figure. Each subpage includes a group of256 columns. Each column is as described with reference to FIG. 2—i.e.,each column has dummy cells 106 and regular storage cells 108 coupled tobit line pairs 110 that are connected to sense amplifiers 112. Asindicated, one or more latches 114 may also be included in each columnto store the sense amplifier output and thereby provide one or moreadditional bits of storage. To simplify the figure, reference numbersare designated only on the first subpage and only a single latch percolumn is shown.

At the row level, the subpage configuration is implemented withsegmented word lines. Specifically, each row has a segmented word linecircuit including a global word line and a plurality of local wordlines. Each local word line is associated with one of the subpages ofthe array. Referring specifically to row 102, segmented word linecircuit 104 includes a global word line (gwl0) and 32 local word lineslwl0.0 through lwl0.31. Among other things, as will be described below,the segmented word line circuits are controllable to cause selection ofonly a portion of the cells in an active row of the array (e.g., turn oncell transistors only in a selected subpage or subpages.)

Decode and select functions are performed by one or more decoders thatselect rows, subpages and columns for various operations. In the presentexample, DRAM array 100 includes a row decoder 120, subpage decoder 122and column selectors 124. DRAM array 100 is thus addressed with row,subpage and column fields. Typically, only one row is selected at atime, so in the case of an array with 256 rows, the row field would beeight bits wide. If only one subpage is selected at a time, the 32subpages would be addressed with a 5-bit field, though implementationsare possible in which more than one subpage is selected at a time. Stillfurther, it will at times be desirable to have all of the subpages ofthe array selected. The 256 individual columns within a subpage may beaddressed with an 8-bit field in order to select a single column.Additional command bandwidth may be provided for multi-I/Oconfigurations in which multiple columns are selected.

A row activate operation will now be described, in which cell chargesare read onto bit lines, bit line values are sensed, and cells arerestored to the charge values present before the destructive read of thecharge on the cell capacitors. To activate a subpage of a row, rowdecoder 120 decodes a row address ROW in order to select a single globalword line gwl(ROW) to go high. In parallel, subpage decoder 122 decodesa subpage address SUBPAGE to generate a subpage select signal thatdrives a single subpage select line sps(SUBPAGE) to go high. These twoasserted signals are ANDed (e.g., with AND gate 126) such that theircoincidence causes a single local word line lwl(ROW.SUBPAGE) to go high,as a result of the subpage select signal gating the global word line.This selects the 256 cells (switches on their transistors) on that rowand in that subpage so that the cell capacitors are connected to andshare their charge with their precharged bit lines. The sps(SUBPAGE)assertion also triggers the associated subpage of sense amplifiers tosense and capture the signal on the bit lines and restore it to fullswing. Once the restored charge is written back to the selected cells,the word line can be lowered.

The column groupings and subpage decoding in FIG. 1 are arbitrary andprovided as an illustrative example; different configurations may beemployed without departing from the spirit of this description. Subpagescan have any practicable number of columns. Additional decode commandbandwidth can be provided to select multiple subpages, instead of one ata time. For example, a power-of-2 scheme could be employed allowing forselection of 2, 4, 8 or 16 of the 32 subpages, In such a case, the arrayprovides variable page width operation, in which the decoder outputdetermines the size of the portion of the row being activated—a firstcontrol can cause a first set of subpages to be activated, with a secondcontrol activating a larger set of subpages. In the most general case,subpage decoding can be implemented as a mask (32 bits in the currentexample) in which any combination and number of subpages can beselected.

The subpage implementation can also allow for targeted prechargeoperations, which can produce significant energy savings. As discussedabove, the row activate operation ends with values being restored acrossthe cell capacitors. Therefore, the precharge operation needs only toprecharge the sense amplifiers and set the dummy cells and bit lines totheir 50% values. The subpage select signals can again be employed sothat the precharge operation only affects the selected columns and theirassociated bit lines, cells, etc. Assuming a read operation on only onesubpage, a subsequent precharge can be limited to that portion of thearray, thereby avoiding expending energy to precharge the columns innon-selected subpages. These savings can be significant given thatactivate and precharge operations can occur at much higher frequenciesthan refresh.

It will be desirable at times to have all subpages selected at the sametime, for example during a refresh operation. In the example of FIG. 1,signaling is provided to activate a global word line and cause all ofthe subpage select lines to go high. This connects all of the cells inthe the row and the appropriate dummy cells to their respective senseamplifiers, which are also triggered by the subpage select lines. Asdescribed above, this causes the appropriate charge to be restored tothe cell, after which the word line is lowered. If an extra latch isprovided for each column, as in FIG. 1, a refresh can be performedwithout enabling the latch, allowing the pages to be held active duringa refresh. Alternatively a special refresh—effectively a global rowactivate—can perform a refresh and enable the latch allowing all of thesubpages of a page to be activated in a single operation.

A column address COLUMN is used in read and write operations. FIG. 1shows column selectors 124 with which such an address may be used. Insingle-bit I/O operations (i.e., reading or writing a single column),COLUMN would be an 8-bit field which, when combined with the subpageaddress SUBPAGE, would specify a particular individual column within adesignated subpage. Once a subpage has been loaded into the senseamplifiers (or the latches if present), the combination of the subpageand column address causes a specific column to be read out onto the databus. These addresses are also used during write operations, to causedata to be loaded from the data bus into specific sense amplifiers orlatches.

When multi-bit I/O is employed (i.e., reading/writing multiple cellssimultaneously), it typically will be desirable to limit the activity toas few subpages as possible, to take advantage of the energy-savingfeatures of the described segmentation. For example, if a 32-bit read isperformed, taking one bit from each sub-page would entail reading 8 kbits into the sense amplifiers. Alternately, the 32 bits could all beread from a single subpage, thereby avoiding the overfetch energyexpenditure needed to read from the other 31 subpages.

This written description uses examples to disclose the invention,including the best mode, and also to enable a person of ordinary skillin the relevant art to practice the invention, including making andusing any devices or systems and performing any incorporated methods.The patentable scope of the invention is defined by the claims, and mayinclude other examples as understood by those of ordinary skill in theart. Such other examples are intended to be within the scope of theclaims.

1. A dynamic random access memory (DRAM) array, comprising: a pluralityof rows; a plurality of columns; a plurality of cells, each beingassociated with one of the columns and with one of the rows, where eachcell includes a capacitor that is selectively coupled to a bit line ofits associated column so as to share charge with the bit line when thecell is selected; and a segmented word line circuit for each row, thesegmented word line circuit being controllable to cause selection ofonly a portion of the cells in that row.
 2. The DRAM array of claim Lwhere for each row, the segmented word line circuit includes: a globalword line; and a plurality of local word lines that are each coupledwith the global word line and an associated subpage of the cells in therow, where the cells of a given subpage are selected to share chargewith their bit lines by (i) asserting the global word line and (ii)gating the asserted global word line with an asserted subpage selectsignal in order to assert the local word line coupled with the givensubpage of cells.
 3. The DRAM array of claim 1, further comprising adecoder configured to generate subpage select signals that control whichbit lines of the DRAM array are involved in a commanded DRAM operation.4. The DRAM array of claim 3, where the commanded DRAM operation is acommand to have cells in a row share the charge of their capacitors withthe bit lines of their associated columns, the subpage select signalstherefore controlling which bit lines are involved in such chargesharing.
 5. The DRAM array of claim 3, where the commanded DRAMoperation is a command to precharge bit lines, the subpage selectsignals therefore controlling which bit lines are precharged.
 6. TheDRAM array of claim 3, further comprising, for each column, a sense ampcoupled to a bit line of the column, and where the commanded DRAMoperation is a command to enable the sense amps to sense charge levelson their coupled bit lines, the subpage select signals thereforecontrolling which sense amps perform such charge sensing.
 7. The DRAMarray of claim 6, where the sense amps are configured to generate anoutput indicative of whether a cell that has shared charge with the bitline was storing a logical HI or logical LO voltage level.
 8. The DRAMarray of claim 7, further comprising a latch coupled to each of thesense amps and operative to store the output of the sense amp.
 9. Adynamic random access memory (DRAM) array, comprising: a plurality ofrows; a plurality of columns; a plurality of cells, each beingassociated with one of the columns and with one of the rows; and adecoder configured to generate subpage select signals that control whichcolumns of the DRAM array are involved in a commanded DRAM operation.10. The DRAM array of claim 9, were each cell includes a capacitor thatis selectively coupled to a bit line of its associated column so as toshare charge with the bit line when the cell is selected, and where thecommanded DRAM operation is a command that selected capacitors in aselected row share charge with their associated bit lines, the specificcapacitor selection being caused by the subpage select signals.
 11. TheDRAM array of claim 9, where each column includes a pair of bit linescoupled with a sense amp, and where the commanded DRAM operation iscommand to precharge selected bit lines, the specific bit line selectionbeing caused by the subpage select signals.
 12. The DRAM array of claim9, where each column includes a pair of bit lines coupled with a senseamp, and where the commanded DRAM operation is a command to enableselected sense amps to sense charge levels on their coupled bit lines,the specific sense amp selection being caused by the subpage selectsignals.
 13. The DRAM array of claim 9, where the decoder iscontrollable to provide variable page width operation such that, for agiven one of the rows, the decoder is operable to activate a portion ofthe row which varies in size based on an output of the decoder.
 14. Adynamic random access memory (DRAM) array, comprising: a plurality ofrows; a plurality of columns; a plurality of cells, each beingassociated with one of the columns and with one of the rows, where eachcell includes a capacitor that is selectively coupled to a bit line ofits associated column so as to share charge with the bit line when thecell is selected; and a segmented word line circuit for each row wherethe segmented word line circuit includes a global word line and aplurality of local word lines that are each coupled with the global wordline and an associated subpage of the cells in the row, where the cellsof a given subpage are selected to share charge with their bit lines by(i) asserting the global word line and (ii) gating the asserted globalword line with an asserted subpage select signal in order to assert thelocal word line coupled with the given subpage of cells.
 15. The DRAMarray of claim 14, further comprising a decoder configured to generatethe subpage select signal.
 16. The DRAM array of claim 15, where thedecoder is further configured to generate signals to select rows andcolumns for use in DRAM operations.
 17. The DRAM array of claim 14,further comprising a plurality of subpage select lines.
 18. The DRAMarray of claim 17, where each of the subpage select lines is associatedwith a subset of the plurality of columns.
 19. The DRAM array of claim18, where for each subset of the plurality of columns, each row has alocal word line for the subpage of cells in those columns, theassociated subpage select line being configured to select the local wordline of the subset of the plurality of columns.
 20. The DRAM array ofclaim 18, where for each subset of the plurality of columns, each columnwithin the subset has a sense amp that is selectively enabled by thesubpage select line associated with the subset of the plurality ofcolumns.
 21. The DRAM array of claim 20, where for each subset of theplurality of columns, each column has a latch coupled to its sense amp,the latch being triggered by the subpage select line associated with thesubset of the plurality of columns.